1. Technical Field
Exemplary embodiments of the present disclosure relate to a memory system including a cache memory, a spare memory, a main memory and so forth.
2. Background Art
A general set-associative cache needs tag matching to determine cache hit/miss of data to be accessed. For tag matching, a cache needs a metadata storage and logic for tag matching. Such logic is very complex and causes an increase in memory system area, and a tag matching operation causes an increase in latency. This requires a cache structure minimizing an increase in the memory system area and an increase in latency.
Recently, research on next-generation memories such as a RRAM (Resistive Random Access Memory), a PCRAM (Phase-Change Random Access Memory), and an MRAM (Magnetic Random Access Memory), and FRAM (Ferroelectric Random Access Memory) has become more active. However, operating speeds of the next-generation memories have not reached a desired speed yet, and fault rates of the next-generation memories have not been reduced to a desired level. Furthermore, the next-generation memories have a problem of low endurance and thus are problematic in that many accesses, rapidly reduces the lifetime of the memory. Therefore, a cache structure which assists in increasing the operating speeds of the next-generation memories and a technology which solves the program of faults of the next-generation memories is required.